Designing a Low Latency 10G Ethernet Core - Part 1 (Introduction)

View the code on GitHub

Links to the other parts in this series:

1. Introduction (this post)
2. Design Overview and Verification
3. Low Latency Techniques
4. Performance Measurement and Comparison
5. Potential Improvements

Introduction

This is the first in a series of blog posts describing my experience developing a low latency 10G Ethernet core for FPGA. I decided to do this as a personal project to develop expertise in low latency FPGA design and high-speed Ethernet, as well as to experiment with tools and techniques that I could use full-time. As a small spoiler, the design has less than 60ns loopback latency, which is comparable to commercial offerings.

These posts will focus on the things that are likely different to a ‘standard’ design, as I believe this will be more interesting to the reader. Specifically:

• The use of cocotb and pyuvm for verification
• The techniques implemented to reduce packet processing latency
• Analysis of commercially available low latency and ‘ultra’-low latency cores
• Latency measurement results and comparison
• Other techniques not implemented

If the reader is unfamiliar with Layer 1/2 Ethernet, I would recommend the following resources:

• 10G Ethernet Layer 1 Overview
• YouTube - The Big MAC Mystery
• IEEE Standard for Ethernet - Full Ethernet (802.3) spec
• 64B/66B overview - Overview of 10G PCS from the spec above

Next Post - Design Overview and Verification